1. Field of the Invention
The present invention relates generally to integrated circuits and, more particularly, to computer automated methods for implementing corrections to geometric feature masks used in photolithography to compensate for optical proximity effects.
2. Description of the Related Art
As the demand for faster, smaller, and more densely packed integrated circuit designs continue to increase, a greater burden is placed on design engineers to improve mask designs. A common technique used to improve mask designs is to modify mask feature geometries in order to compensate for anticipated photolithography optical proximity effects that become more pronounced when device features decrease in size. Generally, the greatest demand for increased density lies in the core region of an integrated circuit design, which requires thousands of closely packed polysilicon gate features. However, the increased density of the polysilicon gate features in the core region is also known to promote optical proximity effects that cause gate shrinkage and other deforming effects. That is, although the polysilicon gate is designed with a sufficient amount of overlap over the diffusion region, the gate shrinkage may produce devices in which the gate does not adequately overlap the diffusion regions.
With this in mind, FIG. 1A shows a cross-sectional view of a substrate 100 having a transistor device 104 fabricated thereon. In this example, the transistor device 104 is formed between shallow trench isolation (STI) regions 102 which are used to isolate neighboring transistors throughout an integrated circuit design. During the fabrication of the transistor device 104, a gate oxide 108 and a polysilicon gate 106 is formed before an impurity implant 112 is performed. As is well known in the art, the impurity implants 112 are performed to form diffusion regions 110a and 110b which will function as either a source or a drain depending upon the wiring of the transistor device 104.
During the design of the polysilicon gate 106, a mask design is created such that the polysilicon gate 106 will extend over the entire width (W) of the transistor device 104 as shown in FIG. 1B. Unfortunately, due to optical proximity effects, the ideal mask design that is used to define the polysilicon gate 106 will experience optical proximity shrinking, rounding, and even alignment tolerances as shown by edge 106b. More specifically, when the polysilicon gate 106 mask was designed, the mask was designed to extend past the width (W) of the diffusion regions 110a and 110b as shown by the ideal mask edge 106a. Although optical proximity shrinking is a commonplace problem in the design of sub-micron technology devices, the optical proximity problems tend to impact transistor device functionality most when shrinkage occurs to the polysilicon gate 106 of core region transistors.
FIG. 1C shows a magnification of the shrinkage and rounding that occurred at the edge 106b of the polysilicon gate 106. Because the transistor gate 106 is no longer extending over the entire diffusion regions 110a and 101b, the subsequent impurity implant 112 will also cause the diffusion region to be formed in region 110'. As a result, the functional characteristics of the transistor device 104 will be severely hampered due to leakage currents that can occur between the diffusion regions 110a and 110b. As pictorially illustrated, the diffusion regions 110a and 110b will only be separated by a resistance "R," which allows the leakage currents to flow between the drain and source even when the transistor device 104 is intended to be in an OFF state. Consequently, an integrated circuit design having transistor devices which conduct current when they are not intended to conduct will disrupt the functionality of the entire integrated circuit.
To combat this known optical proximity effect, a number of optical proximity correction (OPC) software tools have been introduced and are readily used. A couple of exemplary companies that produce OPC software include: (1) Trans Vector Technologies, Inc., of Camarillo, Calif; and (2) OPC Technology, Inc., of San Jose, Calif. Typically, optical proximity correction tools are designed to scan over an entire mask having feature geometries in digital form, and implement a correction at locations which are known to suffer from optical proximity effects. As shown in FIG. 1D, OPC software is typically used to add (or subtract) correction features such as 116a, 116b, and 116c to desired locations on features selected by the OPC software. Unfortunately, performing OPC on selected features of a given design mask in an integrated circuit design requires that the completed mask be completely analyzed by the OPC software, which suggests locations for correction features 116. Depending on the size of the mask, this process can be quite computationally intensive.
Many times, the suggested locations for the correction features are not in the locations in which designers know or anticipate shrinking and rounding to will occur. When that happens, design engineers are required to manually inspect the locations of the suggested correction features and then make adjustments as necessary. Although simplistic in theory, such manual corrections are very laborious because many of today's integrated circuit designs have thousands and some times millions of transistor devices, especially in the core region. Taking for example, the aforementioned shrinkage problem of the polysilicon gate 106, a mask designer would have to manually inspect each edge of a polysilicon gate feature to ensure that the appropriate correction feature has been added to the end of the polysilicon gate 106. This, of course, can take a very long time.
In some instances, as shown in FIG. 1D, a polysilicon gate 106' may not include the proper correction features, which will therefore have to be added by the design engineer whose task it is to inspecting the mask. In sum, although the use of today's optical proximity correction (OPC) software packages have improved the identification of possible optical proximity problem areas, today's OPC software still poses a high degree of burden on a design engineer to manually inspect certain types of critical features throughout an integrated circuit design. Consequently, because shrinkage is so common with the polysilicon gate 106, and the polysilicon gate 106 is an important and critical feature of an integrated circuit design, such features have to be manually inspected and adjusted if necessary, each time a new mask design for the polysilicon gate 106 is designed.
In view of the foregoing, there is a need for methods for automatically correcting critical design features during the initial design phase, which will reduce the need for specialized optical proximity correction techniques and then subsequent manual inspection and laborious correction.